Category: Student Support Unplugged


This space can be utilized for clearing doubts on the concepts of Advanced Operating System PECS 3409 of BPUT Syllabus. Questions will be added to the topic body and answers will be discussed in the comments.

  1. What is consistency maintenance in distributed system and what are its prime categories?
  2. Discuss the technique by which RPCs can be replaced in threaded environment for increasing performance?
  3. What is Omega Network?
  4. Draw 16 input Omega network
    16OmegaNetwork

    16 input Omega Network

     

See this document for other Answers :

Name at least 4(four) different type of processors that can be used as the core of an embedded system.

  • General Purpose Processor (GPP)
    • Microprocessor
    • Microcontroller
    • Embedded Processor
    • Digital Signal Processor
    • Media Processor
  • Application Specific System Processor(ASSP)
  • Multiprocessor system using GPP and ASSPs
  • GPP Core or ASIP core integrated into Application specific Integrated Circuit ASIC orVLSI integrated with processor units on ASIC VLSI Chip.

What is a charge pump? Give at least one example where charge pump is used.

An Internal power source is required for a system. But when a system does not have a power source of its own, they connect to either an external power source or a charge pump.

A charge pump uses arrays of capacitors to increase voltage in a circuit. In this way, you can drive higher voltage loads from logic voltages of 3 – 5 volts. A charge pump consists of a diode in the series followed by a charging capacitor. The diode gets forward bias input from an external signal; for example, from an RTS signal.

A common application for charge pump circuits is in RS-232 level shifters where they are used to derive positive and negative voltages (often +10 V and -10 V) from a single 5 V or 3 V power supply rail.

What is index register and segment register?

Index registers are used to provide more flexibility in addressing modes, allowing the programmer to create a memory address by combining the contents of an address register with the contents of an index register (with displacements, increments, decrements, and other options). In some processors, there are specific index registers (or just one index register) that can only be used only for that purpose. In some processors, any data register, address register, or general register (or some combination of the three) can be used as an index register. Intel 80×86: 7 of the 8 general purpose registers may be used as an index register.

Base registers or segment registers are used to segment memory. Effective addresses are computed by adding the contents of the base or segment register to the rest of the effective address computation. In some processors, any register can serve as a base register. In some processors, there are specific base or segment registers (one or more) that can only be used for that purpose. In some processors with multiple base or segment registers, each base or segment register is used for different kinds of memory accesses (such as a segment register for data accesses and a different segment register for program accesses). These registers are a part of the x86 “Segmentation Memory Model” and are rarely used due to the advent of “flat” memory space. Despite their depreciation during the evolution of the x86 architecture, these registers are still required to have a valid values during normal CPU operation.

What are Virtual Devices? Give two examples of virtual devices.

A virtual device in Unix is a file such as /dev/null or /dev/urandom, that is treated as a device, as far as user level software is concerned, but is generated by the kernel without reference to hardware.

For instance when /dev/null is written to, the kernel tells the program it wrote everything to it (without actually writing it anywhere), and when read from, the reading program is told that it has reached the end of the file. It is a device file (it can be made with mknod for instance), but does not reference any hardware.

File and Pipe are the examples of Virtual devices.

What are the advantages of re-entrant functions in embedded system software?

A reentrant function is one that can be used by more than one task concurrently without fear of data corruption. Conversely, a non-reentrant function is one that cannot be shared by more than one task unless mutual exclusion to the function is ensured either by using a semaphore or by disabling interrupts during critical sections of code. A reentrant function can be interrupted at any time and resumed at a later time without loss of data. Reentrant functions either use local variables or protect their data when global variables are used.

A reentrant function:

  • Does not hold static data over successive calls
  • Does not return a pointer to static data; all data is provided by the caller of the function
  • Uses local data or ensures protection of global data by making a local copy of it
  • Must not call any non-reentrant functions

Advantages :-

  • Embedded systems have space constraints. Reentrant functions reduce space requirements.
  • Maintenance of a single source
  • Proper handling of software interrupts.
  • Avoiding data corruption.

What do you mean by NRE cost in a system design?

Design costs, also called Non-Recurring Engineering costs (NRE), are of major importance when few of a particular embedded system are being built. Conversely, production costs are important in high-volume production. Embedded systems vary from single units to millions of units, and so span the range of tradeoffs between NRE versus production costs.

However with the continuous advancements in electronic design process and in the quality of CAD / CAE tools, NRE costs for simple embedded systems should come down but in reality with the advancement in technology, more and more complex embedded systems are being built which maintains the NRE (development) costs quite high.

What do you mean by Interrupt Latency?

When an electronic device causes an interrupt, the intermediate results (registers) have to be saved before the software responsible for handling the interrupt can run. They must also be restored after that software is finished. If there are more registers, this saving and restoring process takes more time, increasing the latency.

Interrupt Latency Period Tla is a sum of:-

  • Time for response and initiation for ISR instructions. (This includes time to save or switch the context)
  • Periods needed to service all interrupts of higher priority than that of the present one.
  • Maximum period of disabling of the execution of the ISR for “critical region” instructions.

Ways to reduce such context/restore latency include having relatively few registers in their central processing units (undesirable because it slows down most non-interrupt processing substantially), or at least not having hardware save them all (hoping that the software doesn’t then need to compensate by saving the rest “manually”). Another technique involves spending silicon gates on “shadow registers”: one or more duplicate registers used only by the interrupt software, perhaps supporting a dedicated stack.

What do you mean by Priority Inversion?

Priority Inversion is a resource sharing problem in a priority scheduling situation.

Most commercial real-time operating systems (RTOSes) employ a priority-based preemptive scheduler. These systems assign each task a unique priority level. The scheduler ensures that of those tasks that are ready to run, the one with the highest priority is always the task that is actually running. To meet this goal, the scheduler may preempt a lower-priority task in mid-execution. However the scheduler may not have any control over the resources in the system and the resource once allocated to a low priority process will remain allocated to it till release.

This situation may force a high priority process to remain in waiting for the resource to get released. The waiting elongates if another medium priority process pre-empts the low priority process to execute itself. Now the midium priority process is running. The low priority process is in waiting for the midium priority process to finish and high priority process will get a chance to execute only after the lower priority processes finish. This is illogical and improper as ideally the high priority process should finish first. This problem is known as priority inversion problem.

What do you mean by hierarchical RTOS?

Hierarchical RTOS is a configurable RTOS where only limited functions of the scheduler is derived.  All other functions like memory allocation, IPC, Memory Management, File System operations etc are kept outside the scheduler. These functions link and bind dynamically as and when needed. This makes the RTOS use only the functions needed and if required extended. Such a hierarchical RTOS can be configured for specific processors and devices.

What do you mean by hierarchical RTOS?

Hierarchical RTOS is a configurable RTOS where only limited functions of the scheduler is derived.  All other functions like memory allocation, IPC, Memory Management, File System operations etc are kept outside the scheduler. These functions link and bind dynamically as and when needed. This makes the RTOS use only the functions needed and if required extended. Such a hierarchical RTOS can be configured for specific processors and devices.

Enumerate the sequence of events that takes place in interrupt handling.

1. Hardware stacks program counter, etc.
2. Hardware loads new program counter from interrupt vector.
3. Assembly language procedure saves registers.
4. Assembly language procedure sets up new stack.
5. C interrupt service runs (typically reads and buffers input).
6. Scheduler decides which process is to run next.
7. C procedure returns to the assembly code.
8. Assembly language procedure starts up new current process.

What do you mean by plug and play devices? Explain any protocol that supports plug and play feature.

In computing, plug and play is a term used to describe the characteristic of a universal computer bus, or device specification, which facilitates the discovery of a hardware component in a system, without the need for physical device configuration, or user intervention in resolving resource conflicts.
Plug and play refers to both the boot-time assignment of device resources, and to hotplug systems.
ISA PnP or (legacy) Plug & Play ISA was a plug-n-play system that used a combination of modifications to hardware, the system BIOS, and operating system software to automatically manage resource allocations. It was superseded by the PCI bus during the mid-1990s.
UPnP or Universal Plug n Play supports plug and play feature.
Universal Plug and Play (UPnP) is a set of networking protocols promulgated by the UPnP Forum.
Universal Plug and Play functionality involves five processes:
Discovery: A Universal Plug and Play device advertises its presence on the network to other devices and control points by using the Simple Service Discovery Protocol (SSDP). A new control point uses SSDP to discover Universal Plug and Play devices on the network. The information that is exchanged between the device and the control point is limited to discovery messages that provide basic information about the devices and their services, and a description URL, which can be used to gather additional information about the device.
Description: Using the URL that is provided in the discovery process, a control point receives XML information about the device, such as the make, model, and serial number. Additionally, the description process can include a list of embedded devices, embedded services, and URLs that are used to access device features.
Control: Control points use URLs that are provided during the description process to access additional XML information that describes actions to which the Universal Plug and Play device services respond, with parameters for each action. Control messages are formatted in XML and use SOAP.
Eventing: When a control point subscribes to a service, the service sends event messages to the control point to announce changes in device status. Event messages are formatted in XML and use General Event Notification Architecture (GENA).
Presentation: If a Universal Plug and Play device provides a presentation URL, a browser can be used to access interface control features, device or service information, or any device-specific abilities that are implemented by the manufacturer.

What problem might occur in a shared memory process communication? How can you overcome that problem? Illustrate your answer with an example.

Sharing memory for communication between processes is a classical IPC methodology available for operating systems. Here one process creates an area in RAM which can be used by other processes. Since multiple processes can access the shared memory area like regular working memory, this is a very fast way of communication. 2.6 Linux kernel series uses /dev/shm (a world-writable directory that is stored in memory with a defined limit in /etc/default/tmpfs) for shared memory IPC. The program PulseAudio uses it extensively.
Problem arises when there is a multiple-processor architecture. If the Cache-Coherence policy is not adopted, a copy of the shared memory will be running for accessing process which may not be current, eventually leading to over-writing of the shared memory with inaccurate data.
Example: –
Process X and Y handles location L for shared access.

  1. X read L

  2. X Writes L

  3. Y read L

  4. Y Writes L

  5. X read L but this actually is not a read because content of L is already there in cache. As cache coherence is not used the old value is there in L

  6. X writes L now it writes wrong data because the earlier read was not proper and garbage in results in garbage out.

If any Cache-Coherence policy is adopted, the cache will be kept updated for accesses. This would result in updated value in cache.
Otherwise use of cache can be disabled for shared memory locations. This requires too complicated implementations.
An other method is to disable cache altogether. This is not advised as this will seriously impact performance.

MOBILE
short
a)Describe IMEI and its parts.
b)Write about APN and its importance for GPRS.
c)Compare Signal Encryption with Call Encryption.
d)Compare In-band and Out-of-band signaling. Which should be preferred and why?
e)What is Tandem Call?
long
Describe IN Conceptual Model (INCM)
Describe the limitations of GPRS.
Describe GPRS Network Architecture.
EMBEDDED
short
a)What do you mean by a Device? Explain with example.
b)What is Synchronous transmission?
c)Compare Bit Stuffing and Octet Stuffing in HDLC.
d)Describe with example Iso-Synchronous Transmission?
e)Differentiate Standard and Extended HDLC.
long
Describe HDLC frame structure
Compare Synchronous and Asynchronous serial input characteristics.
Short Notes
a)Compare Simplex, Duplex and Half Duplex communication with examples.
b)Classify I/O Devices
I can’t currently upload my notes to the website due to server problem. I will post them here.ES-2-2-HDLC and ES-2-1-Devices.

SPMP Example

Find a good introduction to SPMP document here.

Dear Students,

The new semester brings you the combo pack of SE and ISD in a comprehensive integrated contagious and addictive package packed in the dungeons of Roland that is bound to send a chill down your spine and a smile wide across your faces. Here is the first draft of contents of the combined package.

om-swengg-isd-bcse-3402-bcse-3406

Enjoy reading and “Suggestions” always welcome!!!

Q h 7thECE2006

A logical address space of 12 pages of 1024 bytes each mapped to a physical memory of 64 frames. What would be the minimum number of bits in logical address?

Q i 7thECE2006

What would be the minimum number of bits in physical address?

Q 2 7thECE2006

A demand paged virtual system has the following parameters

  1. Time to serve page faults:
    • When a new frame is allocated: 12 mili seconds
    • When a modified page is replaced: 20 mili seconds
  2. Memory access time: 200 nano seconds
  3. While serving a page fault:
    • Probability of allocating a new frame: 30%
    • Probability of allocating a modified frame: 70%

Find the maximum page fault rate such that degradation in memory access time is not more than 20%.

From Prof. Anthony D. Joseph

  1. Which of the following instructions should be allowed only in kernel mode?
    1. Disable all interrupts
    2. Read the time-of-day clock
    3. Set the time-of-day clock
  2. Five jobs are waiting to be run. Their expected running times are 9, 6, 3, 5, and X. In what order should they be run to minimize average response time? State the scheduling algorithm that should be used AND the order in which the jobs should be run. (Your answer will depend on X)
  3. Consider a system that starts with a total of 150 units of memory, which is then allocated to three processes as shown in the following table of processes, their maximum resource requirements, and their current allocations:
    Process    Max Demand    Currently Holds
    P1           70                  45
    P2           60                  40
    P3           60                  15
    P4           60

    Determine whether it would be safe to grant each ofthe following requests. If YES, give an execution order that could be guaranteed possible. If NO, show the resulting allocation table.

  4. Evaluate the Banker’s algorithm for its usefulness in real life. Give at least two reasons to justify your choice.

The Embedded Battle

Today the PECS 3405 EMBEDDED SYSTEMS paper was over.
Most of the short questions were good; albeit some difficulties in the
longer siblings.


  1. Shorts
    1. List down various hardware and software resources in an embedded computer system.
    2. Why the response time of LINUX is lower that WINDOWS operating system? <<Grammatical Error
    3. What are the parameters used to characterize a real time task?
    4. The performance of hierarchical memory system is faster. Why?
    5. Why embedded systems are realized as real time systems?
    6. Distinguish between hard, soft and firm real time systems?
    7. Distinguish between periodic, aperiodic and sporadic tasks in a RTOS.
    8. List down at least three tools that support the design and development of embedded system.
    9. What do you mean by release time and response time of real-time tasks?
    10. List down various hardware and software drivers used in an embedded system.
  2. Long
    1. Explain the relationship between operating system, computer hardware, system software in an embedded system with the help of a schematic diagram. [4]
    2. What is a system call? Explain the uses of system call in embedded system with an example. [4]
    3. The system calls are implemented as interrupt service routines. Justify. [2]
  3. Long
    1. What do you mean by interface synthesis? Illustrate how the communication time requirements are estimated using process-resource mapping and architectural inputs. [4]
    2. Describe a set of native communication application program interfaces in JAVA for the communication between JAVA and the system-on-chip. [6]
  4. Long
    1. What are various criteria to be considered for processor scheduling in an embedded system? Explain various types of processor scheduling policies with examples. Which of these is followed in LINUX operating system. [5]
    2. Five batch jobs A through E, arrive at a computer center at almost the same time. They have estimated running time of 10, 6, 2, 4 and 8 minutes. Their (externally determined) priorities are 3, 5, 2, 1 and 4 respectively, with 5 being the highest priority. For each of the following algorithms determine the mean process turn-around time, ignore process switching overhead: [5]
      1. Round Robin – assume that the system is multi-programmed and that each job gets its fair share of CPU.
      2. Priority Scheduling – assume that only one job at a time runs, until it finishes. All jobs are completely CPU bound.
      3. First come, first served (run in order 10, 6, 2, 4, 8 ) – ditto –
      4. Shortest job first – ditto –
  5. Long
    1. Discuss the role of tools for the development and debugging of embedded systems. What do you mean by run-control debugging and field debugging. [4]
    2. How does the response time is affected by enabling/disabling interrupts in every kernel service call in a real-time operating system? [3]
    3. Discuss the types of interrupts in embedded C. [3]
  6. Long
    1. A virtual memory system has an address space of 8k words, a memory space of 4k words and page and block sizes of 1k words. The following page reference changes occur during a given time interval. (Only page changes are listed, if the same page is referenced again, it is not listed twice). 4 2 0 1 2 6 1 4 0 1 0 2 3 5 7 Determine the four pages that are resident in main memory after each page reference change if the replacement algorithm used is (i)FIFO (ii)LRU. [5]
    2. Disk requests come into the disk driver for cylinders 10, 22, 20, 2, 40, 6 and 38 in that order. A seek takes 6 msec per cylinder moved. How much seek time is needed for (i) First come, first served, (ii) Closest cylinder next, and (iii) Elevator algorithm (initially moving upward). In all cases the arm is initially at cylinder 20. State advantages and disadvantages for each methods. [5]
  7. Long
    1. Explain briefly different real time operating systems with examples. [4]
    2. What is the primary goal of a real-time operating system? [2]
    3. Why round-robin scheduling policy is appropriate for time-sharing operating systems? Explain with example. [4]
  8. Long
    1. Explain the interprocess communication mechanisms in LINUX. [4]
    2. Discuss the message-based interprocess communication in embedded real-time systems and its appropriate operating system support. [3]
    3. How an optimized communication mechanism can be obtained using message-based interprocess communication. [3]

What do you think?

In the coming odd semesters we are faced with a serious problem. The problem is more philosophical than implementational.

There are two papers in the elective list which has licked away our brains. Not that we are biased for any or we are less in manpower but the matter is more about our students. This batch is one of the best as I have encountered in terms of attention in the class, eagerness to learn and imagination. However that is one of our strengths and it also creates a kind of weakness not to let them down at any cost.

Advanced Operating System is a very good course and students from computer science branch should study it as it would expose them to higher understanding in to the behaviour of OS and its links with the Computer Architecture. The prescribed book Milankovic is a bit quirky though it can be learned in the class.

Information Systems Design is a course which is designed to prepare the students for software projects. You can think that both Software Engineering and Information Systems Design are the theories and Project Lab is the experimentation for these theories. This effectively makes ISD the most important course for any budding software engineer. However there is a twist to the story. There is a compulsory course Software Engineering already in the syllabus. SE and ISD share some parts of the theory but they are not the same wine in two bottles thing. They have many things which are not in common. ISD is mainly software project oriented where as SE shows much a bigger prospective. SE is very wide whereas ISD is very focused.

Having said this, Learning AOS will be getting in touch with an advanced set of OS underpinnings. Whereas ISD opens up a vista of commercial Software Designing practices for the student. AOS targets core computing whereas ISD targets the business software market. Both have their strengths. If SE and ISD were in different semesters possibly there would be no place for arguments but their presence in a single semester is what creates the dilemma.

It is no denying that SE and ISD are similar to a certain extent and share some chapters. So in a single semester there would be repetition of the same concepts for two courses. This effectively translates to easy exam preparation for students who can put a bit extra into SE and master ISD.

In the contra opinion, OS is my favourite subject so I personally would like to offer AOS to my students but my recent rendezvous with OS was not very satisfactory (I have already indicated in my previous post) so if students can’t offer sufficient time for courses then they will be in a real nasty problem. 7th semester will certainly have less time because of frequent campus-placement related activities. It is beyond doubt that we will surely finish the course in the class but if I have to teach only the chalk-board (when most students are absent) then this is pure wastage of AOS and a terrible nightmare for students for their 7th sem exams who has to tear out their hair at the last moment before exams.
Finally with a heavy heart we are offering the course twins, SE and ISD and dropping all our plans about offering AOS, as for every one student who can get into the AOS we can isolate two who will find it even more easier to digest ISD. Whatever we decide will be for the better for all our students, not a couple of brilliant exceptions. The debate will go on possibly till the end of the exams.

— Crack your brains with this issue post rants if you feel like —